The present invention generally relates to methods of polishing metal layers on semiconductor substrates. In particular, the present invention relates to a method of polishing a semiconductor substrate having a copper layer thereon by applying a cleaning composition in a chemical mechanical polishing process. The present invention is applicable to manufacturing integrated circuits having submicron design features and high conductivity interconnect structures.
Integrated circuits are typically formed on substrates, particularly semiconductor substrates, such as silicon wafers, by sequentially depositing and etching conductive, semiconductive and/or insulative layers to ultimately form a plurality of features and devices. The active devices, which are initially isolated from one another, are interconnected to form functional circuits and components through the use of multilevel interconnections.
Interconnection structures typically have a first layer of metallization, comprising a conductive pattern and interwiring spaces, a second level of metallization, and frequently third and subsequent levels of metallization. Interlevel dielectrics, such as doped and undoped silicon dioxide, are used to electrically isolate the different levels of metallization in a silicon substrate. Typically, conductive patterns on different layers, i.e. upper and lower layers, are electrically connected by a conductive plug filling a via hole, while a conductive plug filling a contact hole establishes electrical contact with an active region on a semiconductor substrate, such as a source/drain region. Conductive lines are formed in trenches that typically extend substantially horizontal with respect to the semiconductor substrate. Semiconductor xe2x80x9cchipsxe2x80x9d comprising five or more levels of metallization are becoming more prevalent as device geometries shrink to submicron levels.
A conductive plug filling a via hole is typically formed by depositing an interlayer dielectric on a conductive layer comprising at least one conductive pattern, forming an opening through the interlayer dielectric by conventional photolithographic and etching techniques, and filling the opening with a conductive material, such as tungsten. Excess conductive material on the surface of the dielectric interlayer is typically removed by chemical mechanical polishing (CMP).
CMP is pervasively employed at strategic stages in the fabrication of semiconductor devices to remove topographical irregularities and/or reduce the thickness of a particular layer to achieve planar surfaces and/or thinner layers. Generally, CMP involves subjecting a target surface to mechanical abrasion and chemical action, as with a polishing pad and abrasive chemical slurry, to effect removal of surface materials.
In conventional CMP techniques, a semiconductor substrate in need of planarization and/or thinning is mounted on a carrier or polishing head. The exposed surface of the substrate is then placed against a rotating polishing pad that in turn is mounted on a rotating platen driven by an external driving force. The carrier provides a controllable force, i.e. pressure, urging the substrate against the rotating polishing pad. Additionally, the carrier may rotate to affect the relative velocity distribution over the surface of the substrate. A polishing slurry may be distributed over the polishing pad to provide an abrasive chemical solution at the interface between the pad and substrate.
Typically, polishing slurries contain an abrasive and a mixture of compounds including oxidizers, inhibitors and complexing agents. The slurry initiates the polishing process by chemically reacting with the layer being polished. The polishing process is facilitated by the rotational movement of the pad relative to the substrate as slurry is provided to the substrate/pad interface. The dual mechanisms effect the chemical and mechanical polishing of the target layer. Polishing is continued in this manner until the desired layer is appropriately planarized, thinned, or removed.
In applying conventional planarization techniques, such as CMP, to copper (Cu), it is extremely difficult to achieve a high degree surface uniformity, particularly across a surface extending from a dense array of Cu features, e.g., Cu lines, bordered by an open field. A dense array of metal (Cu) features is typically formed in an interlayer dielectric, such as a silicon oxide layer, by a damascene technique wherein trenches are initially formed. A barrier layer, such as a tantalum (Ta) containing layer is then deposited lining the trenches and on the upper surface of the silicon oxide interlayer dielectric. Cu or a Cu alloy is then deposited by conventional copper or copper alloy forming techniques. Excess Cu or Cu alloy is then removed, by one or more polishing steps including employing different polishing pads under different polishing conditions, the barrier layer and any remaining Cu or Cu alloy is then removed by yet another polishing step. Finally excess slurry and/or particles are removed from the planarized surface by rinsing the substrate, typically with deionized water.
After planarizing and exposing the partially planarized bare metal surface to deionized water, there is a propensity for the metal, particularly a metal layer containing Cu, to from an oxide layer on exposed surfaces thereof, e.g., a nascent or atomic oxide layer forms on the metal surface, particularly when the metal is exposed to air or an aqueous environment. To minimize oxidation of an exposed metal layer before or during CMP, inhibitors have been added to CMP slurries. These inhibitors react and/or complex with the metal forming of a film of the inhibitor on the surface of the metal thereby reducing the availability of the metal surface to oxidants. A nascent oxide layer or an inhibitor layer is particularly problematic, however, in multi-step polishing processes because these layers retards CMP of the bulk target layer thereby increasing the time necessary to complete polishing of the copper layer, reducing through-put and increasing processing costs.
Improved CMP materials and methodology for planarizing and/or thinning layers and thin films associated with smaller-sized design features in semiconductor fabrication is needed which reduce surface imperfections, defects and erosion. There exists a particular need for a CMP process for planarizing Cu and Cu metal alloy layers with reduced dishing, increased surface planarity, increased throughput and reduced manufacturing costs.
An aspect of the present invention is a method of polishing a metal layer on a semiconductor substrate with increased through-put.
Additional aspects and other features of the present invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the invention. The aspects of the invention may be realized and obtained as particularly pointed out in the appended claims.
According to the present invention, the foregoing and other aspects are achieved in part by a method of polishing a metal layer on a semiconductor substrate. The method comprises forming a metal layer having an exposed surface over a semiconductor substrate. The exposed surface of the metal layer can be formed by immediately depositing a metal layer over the semiconductor substrate or by partially polishing the metal layer after it is deposited on the semiconductor substrate.
In accordance with the present invention, the method further comprises applying a cleaning composition to the metal layer to clean the surface of the metal layer; and polishing the cleaned surface of the metal layer. Embodiments of the present invention include polishing the metal layer formed over the semiconductor substrate to expose the surface of the metal layer and then cleaning the exposed surface of the metal layer with the composition by abrading the metal surface with a polishing pad having the cleaning composition thereon and wherein the polishing pad is substantially free of a polishing slurry.
The cleaning composition is useful for removing contaminates, oxides and/or inhibitors that form on exposed surfaces of the metal layer. Embodiments of the present invention include cleaning or stripping the metal surface with an aqueous composition comprising at least one organic acid, e.g. citric acid. The cleaning composition can additionally comprise at least one amine, e.g. ammonium/hydroxide.
Another aspect of the present invention is a method of polishing a copper containing layer, i.e. a layer comprising copper, over a semiconductor substrate. The method comprises: forming a copper containing layer having an exposed surface over the semiconductor substrate; cleaning the exposed surface of the copper containing layer with a cleaning composition; and polishing the cleaned surface of the copper containing layer.
In an embodiment of the present invention, the method comprises: forming a dielectric layer on the semiconductor substrate; forming a barrier layer on the dielectric layer; forming the copper containing layer on the barrier layer; polishing the copper containing layer to expose a surface thereof; cleaning the exposed surface of the copper containing layer; and polishing the cleaned surface of the copper containing layer.
The cleaning composition can be used to remove a native oxide film which immediately forms after depositing a copper containing layer or which immediately forms on the exposed surface of the copper containing layer upon polishing the copper containing layer during a multi-step CMP process. The cleaning composition is useful in removing inhibiting films, such as those formed by the application of benzotriazole. In an embodiment of the present invention, the cleaning composition comprises about 0.2 wt % to about 80 wt % of citric acid and about 0.03 wt % to about 10 wt % of ammonium hydroxide in an aqueous medium, e.g. deionized or distilled water with or without one or more lower alcohols or glycols.